Semiconductor structures comprising three-dimensional arrays of chips or layers have emerged as an important packaging approach. A typical three-dimensional electronic package consists of multiple integrated chips having main planar surfaces laminated together to form a monolithic, multichip module, also referred to as a "stack" or "cube". Two common types of multichip modules are the vertically-extending (or "pancake") stack and the horizontally-extending (or "breadloaf") stack. When completed, a metallization pattern is often provided directly on one (or more) edge surface(s) of the multichip module for operationally interconnecting the semiconductor chips and for electrically connecting the module to external circuitry. This metallization, sometimes referred to herein as "application metal," can include individual electrical connects, bussed electrical connects and multi-level wiring.
FIG. 1 depicts a typical multichip module, generally denoted 10, consisting of multiple semiconductor integrated circuit chips 12 laminated together. An application metal 14 resides on one (or more) side surface of stack 10 for operationally interconnecting the chips and/or for electrical connection of the module to external circuitry. Application metallization 14 includes both individual contacts 16 and bussed contacts 18. Module 10 with metallization 14 thereon, is positioned on an upper surface 21 of a carrier 20, which has its own metallization pattern 22 for connecting thereto. Solder bump interconnection between stack 10 and substrate 20 is commonly employed.
Presently, chip or wafer level burn-in stressing and testing are practiced, as well as burn-in stressing and testing of the resultant stack/carrier package before approval for shipment to a customer. By only testing at the chip and then the package level, significant fabrication time and expense can go into the module without knowing whether a defect has occurred in the fabrication process. To guard against the possibility of a failed package, at least one redundant chip is often provided in the multichip module so that if one of the primary chips in the module is found defective following stack fabrication be "invoked" to provide the electronic circuit package with the desired performance level. This activity is commonly referred to in the art as "sparing."
Presented herein are various novel burn-in stressing and testing approaches to evaluating a multichip module, as well as numerous sparing approaches related thereto.